A memory system may include an array of bit cells, each to store a data bit or logic state. A bit cell may include retention circuitry to assert opposing logic states at first and second storage nodes.
A bit cell may be characterized with respect to a time to perform a write operation, referred to herein as a write response time. Write response time may be slowed by contention between write circuitry and retention circuitry of the bit cell, which may be exacerbated at lower operating voltages, and which may reduce a frequency at which write operations may be performed.
In the drawings, the leftmost digit(s) of a reference number identifies the drawing in which the reference number first appears.